• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    In a communications system comprising multiplexer apparatus for transferring data over any one of a plurality of communications lines, line scanning apparatus is provided to address and enable the transfer of data over any one of the communications lines, which lines are divided into groups characterized by the lines maximum frequency. The apparatus of the invention includes a main address counter which is used primarily to address low speed communication lines and thereby enable the transfer of data thereover, a sub scan counter which is utilized primarily to enable the transfer of data over high speed lines, and a medium speed counter which is utilized in combination with the other counters to address the medium speed lines under certain conditions.
    公开号:SU1093264A3
    申请号:SU731966787
    申请日:1973-10-15
    公开日:1984-05-15
    发明作者:Прингл Антони
    申请人:Ханивелл Информейшн Системз Инк. (Фирма)；
    IPC主号:
    专利说明:

    connected to the fourth input of the first element And and the third and first inputs of the second and sixth elements And, the second input of which is connected to the output of the fifth element And, the outputs of the first and second elements And connected to the first and second inputs of the first OR element, the output of which is connected to the first input of the first trigger and through the first element, NOT to the first input of the seventh element AND, the second input of which is connected to the output of the second element OR, the first second and third inputs of which are connected respectively to the outputs of the third, the fourth and sixth elements And the output of the seventh element And is connected to the second input of the first trigger,
    the first output of which is the third output of the block and connected to the first inputs of the eighth and ninth AND elements, the output of the eighth AND element is the first output of the block, and the second input is NOT connected to the output of the ninth AND element through the second element, the second element is NOT It is the fifth output of the block, the second input of the ninth element I is connected to the output of the second trigger and the first input of the tenth element I, the second of which is connected to the second output of the first trigger, which is the fourth output of the block, the output of the tenth element The third element is NOT connected to the second output of the block,
    one
    The invention relates to a communication system, in particular, to a multiplexer used in this system for unlocking data transmission circuits on corresponding communication lines connected to the system.
    A device containing a unwrapping unit is known to consist of three interconnected blocks in which the switching lines are divided into three groups, so that they can be served at different speeds x 1
    The disadvantage of this device is that during each cycle the scanner only scans each line once.
    The closest to the proposed is a mechanical device in which the switch operates with a different (Ysorostom, supported in a given ratio of G2 3.
    The disadvantage of this device. is that channel recognition is not taken into account and therefore multiple mechanical transmissions must be made in precise synchronization.
    The purpose of the invention is to increase equipment utilization and simplify the design.
    The goal is achieved by the fact that in a multiplex device
    for scanning lines operating at different transmission rates, containing a memory connected bilaterally to data lines divided into groups according to transmission speeds, an address register whose output is connected to the memory address input, a pulse generator, and a control unit, there are three counters, a decoder, AND, OR elements, triggers, with the output of the pulse generator connected to the counting, inputs of the first, second and third counters, the reset inputs of which are connected to the output of the AND output element, the first, second and third inputs of which are connected respectively to the output of the descrambler and the first and second outputs of the second counter, the start input of which is connected to the output of the pulse generator; the discharge outputs of the first, second and third counters are connected respectively to the first inputs of the first, second and third elements And, whose outputs are connected to the corresponding inputs of the element OR whose output is connected to the input of the address register, the first and second memory outputs are connected to the inputs of the first and second triggers, the outputs which, as well as the outputs of the decoder and the first and second outputs of the second counter are connected respectively to the first, second, third, quarter and fifth inputs of the control unit, the first, second, third, fourth and fifth outputs of which are connected respectively to the start inputs of the first The third counters, the second and third inputs of the first, second and third elements AND, the bit outputs of the second counter are connected to the inputs of the decoder. The control unit contains ten AND elements, a node for fixing the line speed, two triggers, two OR elements and three NOT elements — the first inputs of the first, second, third, fourth and fifth AND elements are the quarter-input of the block, the second inputs of the first, the third and fifth elements of AND are the fifth input of the block, the third input of the first and fifth and second inputs of the second elements of AND are the third input of the block, the third input of the third and fourth inputs of the fifth And elements are the first input of the block, the second input the fourth element and is the watts The primary block input, the first and second outputs of the line speed fixing node, are connected respectively to the fourth input of the first element And and the third and first inputs of the second and sixth elements And, the second input of which is connected to the output of the fifth element And, the outputs of the first and second elements And with the first and second inputs of the first element OR, the output of which is connected to the first input of the first trigger and through the first element NOT to the first input of the seventh element AND, the second input of which is connected to the output of the second element OR, first, second The first and third inputs of which are connected respectively to the outputs of the third, fourth and sixth And elements, the output of the seventh And element is connected to the second input of the first trigger, the first output of which is the third output of the block and connected to the first inputs of the eighth and ninth elements And, the eighth output element I is the first output of the block, and the second input is NOT connected to the output of the ninth element AND through the second element, the output of the second element is NOT; to the fifth output of the block, the second input of the ninth AND element is connected to the output of the second trigger and the first input of the 64 tenth element And, the second input of which is connected to the second output of the first trigger ,. which is the fourth output of the block, the output of the tenth element AND via the third element is NOT connected to the second output of the block. FIG. 1 shows a multiplex line scanning device; in fig. 2 - control unit. The device contains a pulse generator 1, counters 2-4, decoder 5, elements AND 6-8, element OR 9 ,. memory 10, memory cells 11, reset element AND 12, address register 13, control block 14, data line groups 15.1-15.3, triggers 16, 17, communication lines 18-27. The control unit (Fig. 2) contains a node 28 for fixing the speed of the line elements I 29-38, elements OR 39, 40, triggers 41, 42, elements -NON 43-45. Memory 10 contains several cells 11, the number of which is equal to the number of lines 13. Each cell 11 of memory 10 contains information related to the data received for transmission, control bits and information about the speed of the next line to be scanned multiplex device. This means that each cell 11 contains at least three sub-cells that contain data to be transmitted, respectively. The speed of the next line is also contained in the sub-cell for each line and this information is transmitted to triggers 16 and 17 by which generates control signals via lines 23. Address 10 is also connected to memory 10, which is connected to receive an address that selects one of the slots 11 in memory 10, so that data can be transmitted along address lines. The cell address is received by register 13 through the element OR 9 and through elements AND 6, 7 and 8 from the main counter 2, the partial scan counter 3 and the average speed counter 4. The pulse generator 1 serves to provide synchronizing pulses that complement each of the counters 2-4 during operation of the device. The incomplete scan counter 3 is also unlocked with synchronizing Pulses and is also supplemented, while the main counter 2 and the average speed counter 4 are only added after receiving control signals from the control unit 14, as shown in FIG. 2. Main counter 2 is a six-bit counter that forms an address that is capable of addressing, for example, 64 lines. The main purpose of counter 2 is to unlock low speed lines 15.1. The half-scan counter 3 is also a six-bit counter, which forms an address of four bits for addressing, for example, up to sixteen high-speed lines 15.3. The fifth bit, formed by the incomplete scan counter 3, forms a signal on line 26, while the sixth bit forms a signal on line 27. These signals are respectively used to indicate that the first four bits of counter 3 are cleared. These signals indicate the corresponding intervals or quadrants of the full scan cycle; When the four bits at the output of counter 3 are in the state of a binary unit, this is decoded by decoder 5, which may simply be an AND element, thereby generating the state of the binary unit output of the quadrant signal on line 25 Medium-speed counter 4 forms an address of five bit, is used in particular to form addresses, for example, up to 32 medium-speed lines during the scan interval. Counter 4 is used to unlock medium-rate lines only under certain conditions. The passage of addresses from counters 2-4 through elements AND 6.7 or 8 is permitted by the corresponding states of the control signals on lines 22, 20 and 21 (+ indicates that the state of the binary unit is unlocked by the device, and that the binary zero state unlocks the device). The address is then received by the register 13, which selects one of the cells 11 of the memory 10. Then, depending on the operations, data is received or transmitted on the address line of the lines 15. The lines may be high-speed, medium-speed or slow, or may be a combination
    such speeds.  There may be up to 64 slow lines used with the system, if high speeds are not used by means of pulse generator 1, one cell 11 of memory 10 is unlocked for a time sufficient for speed or medium speed lines, or up to 32 medium speed if there is no slow or high speed; lines, up to 16 high-speed, if there are no slow or medium-speed lines.  Therefore, each of the mid-speed lines replaces the two slow, while each high-speed replaces the four slow.  Slow lines can transmit or receive data in the frequency range with a maximum frequency of 2700 bps, medium speed 5400 bps and high-speed 10. 800 bps Consequently, there is a 2: 1 and 4: 1 interrelation of the frequencies of the corresponding lines.  The transmission frequency is one of the three maximum frequencies, regardless of the frequency required for a particular line.  For example, in the case of the highest frequencies 5400-10.  800 bps, if the data transmission frequency of a single line is 9000 bps, then in fact this data will be transmitted at the maximum frequency of 10. 800 bps  Frequency grouping of different lines can be both more and less than the specified three groups of frequencies, and the number of lines connected to the device can be more or less than 64 lines.  During one full line scan, high-speed lines must be run four times at equal intervals, while medium-speed lines must be run two times during a full scan.  Slow speed lines require only one start-up or operation during a full scan of all lines.  Consequently, the device uses a scanning device that separates a full scan into a subinterval or quadrant chats.  There may be a different number of subintervals.  During each quadrant, high-speed lines are operated once.  During the first and third quadrants, medium-speed lines are operated and slow lines are operated in an appropriate sequence, which remains after high-speed and medium-speed lines are operated.  Every time the counters get 71 to start the data transfer.  Basically, I counter 2 increments 64 times before it automatically returns to its original position, and counter 4 for average speeds 32 times.  The incomplete scan counter 3 is similar to the main account. 2 is that it completely returns to its original position after incrementing 64 times.  Counters can also be set to the O position (to the reset position) by the state of the binary unit received from the AND 12 reset element at the end of the fourth quadrant.  The low part 3 of the counter 3 is returned to its original position four times within 64 increments of the counter 3.  Therefore, each time the four low bits of counter 3 are set to O ,. 16 increments of counter counts 3 occur.  Each of the 16 samples is determined by a quadrant.  After the first 16 samples, the signal on line 26 (goes into the state of binary one, after the second 16 samples) into the state of binary zero, the signal at output 27 goes to the state of binary one, and so on. d.  until all bits have been reset to their original position at the end of the fourth quadrant.  At the end of each quadrant, the high-order bits of counter 3 are binary units, which then generate a signal on line 25.  At the beginning of the second quadrant, the signal on line 26 is in the state of binary one, which indicates together with the fact that the signal on line 27 is in binary state, this is the second quadrant.  The first quadrant is indicated when both signals on lines 26 and 27 are in the binary zero state.  At the beginning of the third quadrant, the SSCSA sample on line 26 is in the binary zero state and the SSCSB signal on line 27 goes to the binary one state indicating that this is the third quadrant.  At the beginning of the fourth quadrant, the signals on lines 26 and 27 are both in the state of binary 1 indicating that this is the fourth quadrant. First of all, each of the high-speed lines is launched in each quadrant, after which the medium-speed lines and the slow lines are used for the remainder of the time.  As an example, consider a device in which there are six high-speed lines, twelve medium-speed lines and sixteen slow ones.  During the first quadrant, six high-speed lines and ten medium-speed lines are put into operation.  During the second quadrant, six high-speed lines are operated again and the two medium speeds remaining.  Then eight slow lines are operated.  During the third quadrant, high-speed lines and ten medium-speed lines are operated.  During the fourth quadrant, six high-speed lines for the fourth time, in the fast; as the remaining two medium-speed lines are operated again and then the eight remaining slow lines.  Thus, at the end of the chain of quadrants, t. e.  at the end of the full scan of the lines, six high-speed lines are operated four times each, twelve medium speeds twice each, sixteen slow ones each once.  The main address counter 2 is sometimes used to address each type of line, while the partial scan counter 3 can be used to address high-speed and medium-speed line types. The medium rate counter is only started to address memory 10 during the fourth quadrant, if the total number of high-speed and medium-speed lines is more than sixteen.  Each of the counters 2-4 is reset to the zero state at the end of the fourth quadrant, and a full scan is performed again.  Main counter 2 has the ability to count from 1 to 64 (in fact, the counter grows from 0 to 63, after which it returns to the zero state, however, to clarify that each of the counters, after being reset, indicates 1, thereby determining the first line) and the counter 2 are connected to two slow lines.  The counter 2 can be stopped by the control unit 14 for storing the next slow line to be operated.  Counter 3 connects to high-speed lines and counts (the smallest values of bits) from 1 to 16 during each of the four quadrants.  By counter 3, two signals are generated. on lines x 26 and 27, which denote four quadrants.  The medium-speed counter 4 counts from 1 to 32 and can be stopped in the same way as the main counter 2.  Usually, in operation, the main counter 2 always works in the first quadrant and counts from 1 to 16.  At the same time, the incomplete scan counter 3 also counts from 1 to 16.  In order to simplify the design of the device, high-speed lines assume the lowest numerical designations, which means that high-speed lines are denoted by 1, although in this example there are six high-speed lines, and medium-speed lines are then denoted by the following numbers 7-18, sequentially for 12 medium-speed lines.  Slow lines accept subsequent numeric characters.  At the end of the first quadrant, if there are any high-speed lines in the system, counter 3 is selected for the next count.  Also at this time, the main counter 2 stops and the four dropped bits of the incomplete scan counter 3 are automatically reset to their initial state. In this way, high-speed lines are scanned and the next slow speed or slow line is read.  During the second quadrant, the incomplete scan counter 3 runs until it is recognized that the next line is not a high-speed line, as indicated by the signals on lines 23 and 24, which have the following binary states, respectively, for slow lines 0, 0; for medium speeds 1.0; for high speed 1.1.  Main counter 2 is then turned on if the next is not a high-speed line.  At the end of the second quadrant, if there are high-speed or medium-speed lines, the incomplete scan counter 3 is selected to start the lines at the beginning of quadrant three and main counter 2 stops.  During the third quadrant, the incomplete scan counter 3 operates until the signal on line 23410 indicates that the next line is not high-speed or medium-speed.  For most systems, the incomplete scan counter 3 controls or unlocks both the mid-speed and high-speed lines, so that the Mid-speed counter 4 is never turned on through the AND 8 element until the number of high-speed and mid-speed lines in combination exceeds sixteen.  Typically, at the end of the third quadrant, main counter 2 stops again and partial scan counter 3 is selected for scanning high-speed lines at the beginning of the fourth quadrant.  However, if the total number of high-speed and medium-speed lines is more than 16, as in the example, an average fast response counter is required.  in this case there will be several medium-speed lines for operation in the fourth quadrant after high-speed lines are first operated.  Under these conditions, counter 3 is selected for the full third quadrant.  At the beginning of the fourth quadrant, the incomplete scan counter 3 automatically returns to its original state and serves high-speed lines, while the average speed counter is stopped.  The control unit 14 remembers that there are still medium-speed lines for operation.  When the signal on line 24 indicates that the next line is not high-speed, the average speed counter 4 turns on and addresses memory 10 until the signal on line 23 indicates that the next line is a slow line.  Finally, main counter 2 addresses the remaining slow lines to transmit data.  The control unit 14 contains a trigger 41, which, after returning to the initial state, generates the state of the binary unit on line 20.  At the beginning of the first quadrant, t. e.  under initial conditions, the signals on lines 18 and 19 are in the state of binary one.  The main counter 2 and the average speed counter 4 are started, the counters 2 and 4 count the clock pulses of the generator 1, the partial scan counter 3 is also started by the pulse generator 1.  Ex.) Initial conditions, the signal on line 20 is in the state of binary one and the signal on line 22 is in the state of binary unit, thus unlocking the ANDb element, allowing the main counter 2-address, memory 10 through the register 13n OR element 9, the signal on line 20 is in the state of binary one since trigger 41 is initially reset to the initial state at the end of the fourth quadrant.  Trigger 42 is also returned to its original state, thereby generating a binary zero state at the input of the AND 37 element and a binary one state at the output of the HE element 44.  Corresponding during the first count of the clock pulses, as in 1. but in this example, the main counter 2 has a signal 1 at the output, the average speed counter 4 and the partial scan counter 3 also have output 1 and the first line is started to transmit data on the first high-speed line.  The selected counter is the main address counter 2 and the count continues to 16 during the first quadrant. During this time, six high-speed lines and ten of the twelve medium-speed lines are triggered before the total data.  At the end of the first quadrant, the signal on line 20 transitions to the binary zero state.  This is because the trigger 41 is set through the EPI element 39, since the element 30 is open.  Unlocking the element AND 30 or 29 locks the element AND 35 by means of the element NO 43.  Element I 30 is unlocked, since node 28 of the line speed fixation indicates that the line is precisely high-speed and due to the generation of signals on lines 26 and 25.  The node 28 fixing the speed of the line (which can be two triggers) initially fixes the speed of the fastest line.  In the example, the fastest operating line is high-speed and, accordingly, the signals at its outputs are in the state of binary one.  The signals from the first and second outputs of node 28 are respectively the following binary states: for slow lines 0.0; for speeds of 0.1.  A signal on line 26 indicates that this is the first or third quadrant, while a signal on line 27 indicates that it is the end of a quadrant.  Since the flip-flop 41 is set to a predetermined state, the signal on the line 18 enters the binary zero state due to (Lock the AND 36 element.  Accordingly, the main counter 2 is stopped.  Therefore, at the beginning of the second quadrant, the main address counter 2 is locked and an incomplete scan counter 3 is selected to address the memory 10 by unlocking the item.  And 7.  Accordingly, at the beginning of the second quadrant, the synchronization pulses arrive at the main counter 2, the average speed counter 4 and the incomplete scan counter 3 sixteen times and the line scan raster indicate that the first six lines are unlocked by the incomplete scan counter 3.  When it is recognized that the next line to be unlocked is not high-speed, AND 32 is unlocked by the signals on lines 24 and 26, this indicates that this is the second quadrant, respectively, since AND 32 is unlocked, trigger 41 is set repeatedly to the initial state through the element OR 40 and unlocks the element AND 35.  The other input signals of AND 35, which are the output signals of the HE 43 element, are in the state of binary 1, since none of the conditions for unlocking the AND elements 30 or 29 is fully satisfied.  Accordingly, by resetting the flip-flop 41, the signal on line 20 enters the state of binary one.  The state of the binary unit of signals on lines 20 and 22 then starts addressing memory 10 through main counter 2.  Signal. on line 18, the tagak goes into the state of a binary unit due to. unlock element 36.  , During the first seven counts of the second quadrant sync pulses, t. e.  the number of samples of the clock pulses 17-23, the main address counter 2 indicates the address 17.  The average speed counter 4 indicates address 23 on the seventh count of the second quadrant, while the incomplete scan counter 3 indicates address 7.  Accordingly, since the main address counter 2 is selected, the seventeen lines are opened.  The main address counter 2 continues to operate during the remainder of the second quadrant, at the end of which the link starts.  It should be noted that the seventeen and eighteen lines are the remaining two medium speeds that can be launched during the first quadrant.  Lines nine-twelve through twenty-six are the first eight slow lines.  As will be seen, the remaining eight slow lines are addressed at the end of the fourth quadrant.  At the end of the second quadrant, if there are high-speed or medium-speed lines, the incomplete scan counter 3 addresses memory 10 and the main counter 2 stops at address 27.  This is because trigger 41 is enabled.  The trigger 41 is turned on, since the AND element 29 is unlocked by signals on lines 26 and 27, which indicate that this is the second quadrant; a signal on line 25 indicates that this is the end of a quadrant, and a signal on the first output of node 28 indicates that all lines are not slow.  Since the signal on line 20 is in the binary zero state, it blocks AND 36 and, accordingly, the state of the signal on line 18 is the binary zero state, thereby stopping the main address counter 2. Therefore, at the beginning of the third quadrant, the incomplete scan counter 3 is triggered via the AND 7 element to address the memory 10.  The main address counter is stopped.  When the clock pulses are counted from 33 to 48, the partial scan counter 3 and the average speed counter 4 are incremented from one to sixteen while the main address counter 2 is stopped at count 27.  The lines triggered by the incomplete scan counter 3 are high speed and the first ten medium-speed lines.  At the end of the third quadrant, the H 30 element opens again, since the fastest line is high-speed and since this is the end of the third quadrant, the trigger 41 is thus set and the signal on the line 20 4 goes to the state of the binary unit, partially unlocking the And 33 .  Also at the end of the third quadrant, AND 33 is unlocked, since signals are generated on lines 26 and 27, which indicate that this is exactly the third quadrant, the signal on line 25 indicates that this is the end of the third quadrant.  The next line is medium-speed or high-speed, as indicated by the signal on line 23.  Unlocking an AND 33 element partially unlocks the AND 34 element and sets the trigger 42, which completely unlocks the AND 38 element and causes a binary zero state at the output of the HE element 45.  The signal on line 18 forces the average speed counter 4 to stop.  Since the signal on line 20 is in the state of binary one and the element 37 is locked, the signal on line 22 is in the state of binary 1, element 7 is unlocked and the partial scan counter 3 is selected at the beginning of the fourth quadrant, thereby allowing the counter 3 incomplete scan Well address memory 10. At the beginning of the fourth quadrant, the first six lines are launched, t. e.  high speed.  During the launch of these lines in the fourth quadrant, the counting of the clock pulses increases from 49 to 54, the main address counter 2 remains stopped at the count 27 and the partial scan counter 3 counts from 1 to 6, thus the memory address 10 and the first six lines are started.  The average speed counter 4 remains stopped on the seventeenth line.  When it is recognized that the next line is not high-speed, AND 32 is unlocked, since the signal on line 24 is in the binary zero state and the signal on line 26 is in the binary one state, indicating that this is the fourth quadrant .  This returns to the initial state the trigger 41, forcing the signal on the line 20 to change to the state of the binary one.  Since the signal at the output of flip-flop 42 remains in the state of binary one, the element 37 is unlocked respectively, and the signal on the line 22 changes to the binary zero state.  Respectively
    with single signals on lines 22 and 20, element 8 is removed and allows the average speed counter 4 to address memory 10. At the time that element 8 is unlocked, the signal on line 19 goes to the state of binary 1, allowing counter 4 to work This is because the binary zero state of the signal on line 22 locks the AND 38 element, causing a binary unit to appear at the output of the HE 45 element. Consequently, after it is recognized that the next line is not 1 high-speed, in the fourth quadrant is elected with 4 is average speed and it addresses the seventeenth and eighteenth medium-speed lines. At the same time, the incomplete scan counter 3 adds to the count of 8 the corresponding 56 sync reverse pulses. Thus, average speed counter 4 is stopped at the end of the third quadrant, thereby allowing counter 3 to address the remaining velocity lines in the fourth quadrant.
    When it is recognized that the next line to be launched is neither the high-speed nor the medium-speed line, i.e. the next line is slow, the trigger 42 is reset by the signal on line 23, thereby locking the AND 37 element to get the state of the binary signal on line 22 and accordingly unlocking the AND element, so that the main address counter 2 can address the memory 10. At this time, the signal on line 18 is in the state of a binary unit, allowing the average speed counter 4 action 4 to continue to increment together with the partial scan counter 3 and the main address counter 2. Since counter 2 is on , The remaining eight medlen5 cruise lines are driven during the remaining portion of the fourth quadrant. Therefore, the combination of high-speed, medium-speed and slow lines in this system can
    0 to be scanned or triggered with a full scan cycle incrementing three counters connected to address memory 10, under the control of the control unit 14 in response
    5 to the signal of the line-speed-fixing unit 28, which are pre-established for a separate device circuit, the signals of the next-line-fixing node, which
    0 may vary.
    Thus, the present invention allows to simplify the device and increase the utilization rate of the equipment.
    权利要求:
    Claims (2)
    [1]
    1. MULTIPLEX DEVICE FOR SCANNING LINES OPERATING WITH VARIOUS TRANSMISSION SPEEDS, containing memory connected by two-way communication with data lines divided into groups according to at a baud rate, the address register, the output of which is connected to the memory address input, is a generator. pulses and a control unit, characterized in that, in order to increase the utilization rate of the equipment and simplify the device, it contains three counters, a decoder, AND, OR elements, triggers, and the output of the pulse generator is connected to the counting inputs of the first, second and third counters, the reset inputs of which are connected to the output of the AND element of reset, the first, second and third inputs of which are connected respectively to the output of the decoder and the first and second outputs of the second counter, the start input of which is connected to the output of the generator A pulse pulse, the discharge outputs of the first, second and third counters are connected respectively to the first inputs of the first, second and third AND elements, the outputs of which are connected to the corresponding inputs of the OR element, the output of which is connected to the input of the address register, the first and second memory outputs are connected to the inputs the first and second triggers, the outputs of which, as well as the outputs of the decoder and the first and second outputs of the second counter, are connected respectively to the first, second, third, fourth and fifth inputs of the control unit, the first Ora, third, fourth, fifth outputs which are connected respectively with soot- §. the start inputs of the first, third counters, the second and third inputs of the first, second and third elements AND, the bit outputs of the second counter are connected to the inputs of the decoder.
    [2]
    2. The device pop. 1, characterized in that the control unit contains ten AND elements, a line speed fixing unit, two triggers, two OR elements and three NOT elements, the first inputs of the first, second, third, fourth and fifth elements AND being the fourth input of the block, the second the inputs of the first, third and fifth elements And are the fifth input of the block, the third input of the first and fifth and second input of the second elements And are the third input of the block, the third input of the third and fourth input of the fifth elements And are the first input of the block, the second input is the fourth AND gate is the second input unit, the first and second output node line speed fixing
    SU, „> 1093264 are connected respectively to the fourth input of the first AND element and the third and first inputs of the second and sixth AND elements, the second input of which is connected to the output of the fifth AND element, the outputs of the first and second AND elements are connected to the first and second inputs of the first OR element, the output of which is connected to the first input of the first trigger and through the first element, NOT to the first input of the seventh AND element, the second input of which is connected to the output of the second OR element, the first; the second and third inputs of which are connected respectively to the outputs of the third, fourth and sixth elements AND, the output of the seventh element And is connected to the second input of the first trigger, the first output of which is the third output of the block and connected to the first inputs of the eighth and ninth H 'elements , the output of the eighth element AND is the first output of the block, and the second input through the second element is NOT connected to the output of the ninth element And the output of the second element is NOT the fifth output of the block, the second input of the ninth element And is connected to the output cerned flop and the first input of the tenth AND gate, the second vkod which is connected to the second output of the first flip-flop, which is the fourth output block, the output of the tenth AND gate through a third element is coupled to the second output unit.
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    US4017688A|1977-04-12|Method and devices for inserting additional pattern in, or removing same from, a message
    US3740475A|1973-06-19|Apparatus for producing coding pulse sequences
    US3627928A|1971-12-14|Telegraph privacy system
    EP0201634A1|1986-11-20|Digital word generator for automatically generating periodic permanent signals from n bit words of all weights and their permutations
    US6804316B1|2004-10-12|Methods and system for performing frame recovery in a network
    同族专利:
    公开号 | 公开日
    DE2351890A1|1974-04-18|
    US3814860A|1974-06-04|
    SE396526B|1977-09-19|
    AU5946473A|1975-02-27|
    GB1443717A|1976-07-21|
    JPS4974853A|1974-07-19|
    FR2203235B1|1976-10-01|
    JPS5750102B2|1982-10-26|
    AU474985B2|1976-08-05|
    CA1008193A|1977-04-05|
    IT994386B|1975-10-20|
    CH587593A5|1977-05-13|
    FR2203235A1|1974-05-10|
    NL7313462A|1974-04-18|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    NL288425A|1962-02-01|
    US3389225A|1964-05-15|1968-06-18|Itt|Limited capacity telephone system|
    JPS4428325Y1|1965-09-07|1969-11-25|
    JPS4525409Y1|1967-02-21|1970-10-05|
    FR2044302A6|1969-05-14|1971-02-19|Cit Alcatel|
    NL7009245A|1970-06-24|1971-12-28|
    JPS5026245B1|1970-06-29|1975-08-29|
    GB1303270A|1970-09-02|1973-01-17|
    FR2122102A5|1971-01-11|1972-08-25|Siemens Spa Italiana|
    DE2110795A1|1971-03-06|1972-09-14|Siemens Ag|Device for transmitting signals of different bandwidths over a common transmission path|US3892925A|1974-06-03|1975-07-01|Ibm|Electric signal exchange switching arrangement|
    JPS576527B2|1974-06-29|1982-02-05|
    JPS5191779A|1974-06-29|1976-08-11|
    JPS5752525B2|1974-06-29|1982-11-08|
    US4121055A|1977-06-06|1978-10-17|Microcom Corporation|Integrated programmable commutation and signal conditioning circuit|
    JPS5747480B2|1977-11-26|1982-10-09|
    DE3171648D1|1980-02-29|1985-09-12|Ibm|Tdma satellite communications system|
    JPS5677776A|1980-11-10|1981-06-26|Seikosha Co Ltd|Photoelectric detecting device|
    GB2157921B|1984-04-19|1987-09-09|Motorola Israel Ltd|Multiplexer/demultiplexer|
    JPS6166803U|1984-10-05|1986-05-08|
    FR2587861B1|1985-09-23|1987-11-13|Devault Michel|BUS ALLOCATOR DISTRIBUTED TO ASYNCHRONOUS DATA SOURCES|
    US5164940A|1991-05-31|1992-11-17|Mitel Corporation|Modular communication system with allocatable bandwidth|
    JP2011506691A|2007-12-19|2011-03-03|中国科学院▲寧▼波材料技▲術▼▲与▼工程研究所|Polythioetherimide and process for producing the same|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US00298078A|US3814860A|1972-10-16|1972-10-16|Scanning technique for multiplexer apparatus|
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